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Micrel, Inc.
2.5V/3.3V 1.5GHz PRECISION LVPECL PROGRAMMABLE DELAY
Precision Edge(R) SY89295U Precision Edge(R)
SY89295U
FEATURES
s Precision LVPECL programmable delay line s Guaranteed AC performance over temperature and voltage: * > 1.5GHz fMAX * < 160ps rise/fall times s Low-jitter design: * < 10psPP total jitter * < 2psRMS cycle-to-cycle jitter * < 1psRMS random jitter s Programmable delay range: 3.2ns to 14.8ns in 10ps increments s Increased monotonicity over the MIC100EP195 s 10% of LSB INL s VBB output reference voltage s Parallel inputs accepts LVPECL or CMOS/LVTTL s Low voltage operation: 2.5V 5% and 3.3V 10% s Industrial -40C to +85C temperature range s Available in 32-pin (5mm x 5mm) MLFTM and 32-pin TQFP packages Precision Edge(R)
DESCRIPTION
The SY89295U is a programmable delay line that delays the input signal using a digital control signal. The delay can vary from 3.2ns to 14.8ns in 10ps increments. In addition, the input signal is LVPECL, uses either a 2.5V 5% or 3.3V 10% power supply, and is guaranteed over the full industrial temperature range (-40C to +85C). The delay varies in discrete steps based on a control word. The control word is 10-bits long and controls the delay in 10ps increments. The eleventh bit is D[10] and is used to simultaneously cascade the SY89295U which allows for a larger delay range. In addition, the input pins IN and /IN default to an equivalent low state when left floating. Further, for maximum flexibility, the control register interface accepts CMOS or TTL level signals. For applications that requires an analog delay input, see the SY89296L which is a programmable delay chip with fine tune control. The SY89295U and SY89296U are part of Micrel's high-speed, Precision Edge(R) product line. All support documentation can be found on Micrel's website at www.micrel.com.
APPLICATIONS
s Clock de-skewing s Timing adjustments s Aperture centering
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. M9999-011806 hbwhelp@micrel.com or (408) 955-1690
Rev.: C Amendment: /0
1
Issue Date: January 2006
Micrel, Inc.
Precision Edge(R) SY89295U
PACKAGE/ORDERING INFORMATION
D7 D6 D5 D4 GND D3 D2 D1
Ordering Information(1)
GND D0 VCC Q /Q VCC VCC NC
32 31 30 29 28 27 26 25
D8 D9 D10 IN /IN VBB VEF VCF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
Part Number SY89295UMI SY89295UMITR(2) SY89295UTI SY89295UTITR(2) SY89295UMG(3)
Package Type MLF-32 MLF-32 T32-1 T32-1 MLF-32
Operating Range Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
Package Marking SY89295U SY89295U SY89295U SY89295U SY89295U with Pb-Free bar-line indicator SY89295U with Pb-Free bar-line indicator SY89295U with Pb-Free bar-line indicator SY89295U with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu Pb-Free NiPdAu Pb-Free NiPdAu
GND LEN SETMIN SETMAX VCC /CASCADE CASCADE /EN
SY89295UMGTR(2, 3) MLF-32 SY89295UTG(3) SY89295UTGTR(2, 3) T32-1 T32-1
32-Pin MLFTM (MLF-32)
D7 D6 D5 D4 GND D3 D2 D1
32 31 30 29 28 27 26 25 D8 D9 D10 IN /IN VBB VEF VCF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 GND D0 VCC Q /Q VCC VCC NC
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
32-Pin TQFP (T32-1)
TRUTH TABLES
Input/Output Inputs IN 0 1 /IN 1 0 OUT 0 1 Outputs /OUT 1 0 Digital Control Latch LEN 0 1 Latch Action Pass Through D[10:0] Latched D[10:0]
Input Enable /EN 0 1 Q, /Q IN, /IN Delayed Latched D[10:0]
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GND LEN SETMIN SETMAX VCC /CASCADE CASCADE /EN
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Micrel, Inc.
Precision Edge(R) SY89295U
FUNCTIONAL BLOCK DIAGRAM
IN /IN /EN 512 GD
0 1
0 1
0 1
0 1
0 1
256 GD
128 GD
64 GD
32 GD
0 1
0 1
0 1
0 1
0 1
16 GD
8 GD
4 GD
2 GD
1 GD
D[9:0] LEN SETMIN SETMAX 1 GD 10-bit Latch Q /Q
0 1
D[10]
CASCADE Latch /CASCADE
VBB VCF VEF
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Precision Edge(R) SY89295U
PIN DESCRIPTION
Pin Number 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 Pin Name D[9:0] Pin Function CMOS, ECL, or TTL Control Bits: These control signals adjust the delay from IN to Q. See "AC Electrical Characteristics" for delay values. In addition, see "Interface Applications" section which illustrates the proper interfacing techniques for different logic standards. D[9:0] contains pull-downs and defaults LOW when left floating. D0 (LSB), and D9 (MSB). See "Typical Operating Characteristics" for delay information. CMOS, ECL, or TTL Control Bit: This bit is used to cascade devices for an extended delay range. In addition, it drives CASCADE, and /CASCADE. Further, D[10] contains a pulldown and defaults LOW when left floating. LVPECL/ECL Signal Input: Input signal to be delayed. IN contains a 75k pull-down and will default to a logic LOW if left floating. Reference Voltage Output: When using a single-ended input signal source to IN or /IN, connect the unused input of the differential pair to this pin. This pin can also be used to rebias AC-coupled inputs to IN and /IN. When used, de-couple to VCC using a 0.01F capacitor, otherwise leave floating if not used. Maximum sink/source is 0.5mA. Reference Voltage Output: Connect this pin to VCF when D[9:0], and D[10] is ECL. Logic Standard LVPECL CMOS TTL 8 9, 24, 28 10 11 VCF GND, Exposed Pad(2) LEN SETMIN VCF Connects to VEF,(1) No Connect 1.5V Source
3
D10
4, 5 6
IN, /IN VBB(1)
7
VEF
Reference Voltage Input: The voltage driven on VCF sets the logic transition threshold for D[9:0], and D[10]. Negative Supply: For MLFTM package, exposed pad must be connected to a ground plane that is the same potential as the ground pin. ECL Control Input: When HIGH latches the D[9:0] and D[10] bits. When LOW, the D[9:0] and D[10] latches are transparent. ECL Control Input: When HIGH, D[9:0] registers are reset. When LOW, the delay is set by SETMAX or D[9:0] and D[10]. SETMIN contains a pull-down and defaults LOW when left floating. ECL Control Input: When SETMAX is set HIGH and SETMIN is set LOW, D[9:0] = 1111111111. When SETMAX is LOW, the delay is set by SETMIN or D[9:0] and D[10]. SETMAX contains a pull-down and defaults LOW when left floating. Positive Power Supply: Bypass with 0.1F and 0.01F low ESR capacitors. LVPECL Differential Output: The outputs are used when cascading two or more SY89295U to extend the delay range. LVPECL Single-Ended Control Input: When LOW, Q is delayed from IN. When HIGH, Q is a differential LOW. /EN contains a pull-down and defaults LOW when left floating. LVPECL Differential Output: Q is a delayed version of IN. Always terminate the output with 50 to VCC - 2V. See "Output Interface Applications" section. No Connect.
12
SETMAX
13, 18, 19, 22 14, 15 16 20, 21 17
Notes:
VCC /Cascade, Cascade /EN /Q, Q NC
1. Single-ended operation is only functional at 3.3V. 2. MLFTM package only.
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) .................................. -0.5V to +4.0V Input Voltage (VIN) ......................................... -0.5V to VCC LVPECL Output Current (IOUT) Continuous ......................................................... 50mA Surge ................................................................ 100mA Lead Temperature (soldering, 20 sec.) ................... +260C Storage Temperature Range (TS) ............ -65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) .............................. +2.375V to +3.6V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance(3) MLFTM (JA) Still-Air ............................................................. 35C/W MLFTM (JB) Junction-to-Board ............................................ 28C/W TQFP (JA) Still-Air ............................................................. 28C/W TQFP (JB) Junction-to-Board ............................................ 20C/W
DC ELECTRICAL CHARACTERISTICS(4)
TA = -40C to 85C, unless otherwise stated. Symbol VCC IEE VIN VDIFF_IN VIHCMR Parameter Power Supply Power Supply Current Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (IN, /IN) Input High Common Mode Range Condition VCC = 2.5V VCC = 3.3V No load, max VCC See Figure 1a. See Figure 1b. IN, /IN 150 300 VEE+1.2 Min 2.375 3 Typ 2.5 3.3 Max 2.625 3.6 220 1200 2400 VCC Units V V mA mV mV V
VCC = 3.3V, TA = -40C to 85C, unless otherwise stated. Symbol VIH VIL VBB VEF VCF Parameter Input High Voltage (IN, /IN) Input Low High Voltage (IN, /IN) Output Voltage Reference Mode Connection Input Select Voltage Condition Min 2.075 1.355 1.775 1.9 1.55 1.875 2.0 1.65 Typ Max 2.420 1.675 1.975 2.1 1.75 Units V V V V V
VCC = 2.5V, TA = -40C to 85C, unless otherwise stated. Symbol VIH VIL VBB VEF VCF
Notes: 1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Rating" conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Thermal performance on MLFTM packages assumes exposed pad is soldered (or equivalent) to the device most negative potential (GND). 4. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. Input and output parameters vary 1:1 with VCC, with the exception of VCF. M9999-011806 hbwhelp@micrel.com or (408) 955-1690
Parameter Input High Voltage (IN, /IN) Input Low High Voltage (IN, /IN) Output Voltage Reference Mode Connection Input Select Voltage
Condition
Min 1.275 0.555 1.175 1.10 1.15
Typ
Max 1.62 0.875
Units V V V V V
1.075 1.20 1.25
0.975 1.30 1.35
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Micrel, Inc.
Precision Edge(R) SY89295U
LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS(5)
VCC = 3.3V; RLOAD = 50 to VCC-2V; TA = -40C to +85C, unless otherwise stated. Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage (Q, /Q) Output LOW Voltage (Q, /Q) Output Voltage Swing (Q, /Q) Differential Output Voltage Swing (Q, /Q) See Figure 1a. See Figure 1b. Condition Min 2.155 1.355 550 1.1 Typ 2.280 1.480 800 1.6 Max 2.405 1.605 Units V V mV V
LVPECL OUTPUTS DC ELECTRICAL CHARACTERISTICS(5)
VCC = 2.5V; RLOAD = 50 to VCC-2V; TA = -40C to +85C, unless otherwise stated. Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage (Q, /Q) Output LOW Voltage (Q, /Q) Output Voltage Swing (Q, /Q) Differential Output Voltage Swing (Q, /Q) See Figure 1a. See Figure 1b. Condition Min 1.355 0.555 550 1.1 Typ 1.480 0.68 800 1.6 Max 1.605 0.805 Units V V mV V
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(6)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to +85C, unless otherwise stated. Symbol VIH VIL IIH IIL
Notes: 5. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. VOH and VOL parameters vary 1:1 with VCC. 6. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max
Units V
0.8 40 -300
V A A
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Precision Edge(R) SY89295U
AC ELECTRICAL CHARACTERISTICS(7)
TA = -40C to +85C; unless otherwise stated. Symbol fMAX tpd Parameter Maximum Operating Frequency Propagation Delay IN to Q; D[0-10]=0 IN to Q; D[0-10]=1023 /EN to Q: D[0-10]=0 D10 to CASCADE Programmable Range tpd (max) - tpd (min) Duty Cycle Skew Step Delay tPHL - tPLH D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High D0-D9 High Note 9 D to LEN D to IN /EN to IN LEN to D IN to /EN /EN to IN SETMAX to LEN SETMIN to LEN Note 13 Note 14 Note 15 20% to 80% (Q) 20% to 80% (CASCADE) 50 90 45 85 Note 10 Note 11 Note 12 -10 200 350 300 200 400 500 500 450 2 10 1 160 300 55 Note 8 10 15 35 70 145 290 575 1150 2300 4610 9220 +10 Condition Clock VOUT 400mV Min 1.5 3200 11500 3400 350 8300 25 4200 14800 4400 670 Typ Max Units GHz ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps %LSB ps ps ps ps ps ps ps ps psRMS psPP psRMS ps ps %
tRANGE tSKEW t
INL tS
Integral Non-Linearity Setup Time
tH tR
Hold Time Release Time
tJITTER
Cycle-to-Cycle Jitter Total Jitter Random Jitter Output Rise/Fall Time Duty Cycle
tr, tf
Notes: 7. High frequency AC electricals are guaranteed by design and characterization. 8. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output. 9. INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay - measured minimum delay) / 1024. INL = measured delay - measured minimum delay + (step number x TIL). 10. This setup time defines the amount of time prior to the input signal. The delay tap of the device must be set. 11. This setup time defines the amount of the time that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than 75mV to the IN, /IN transition. 12. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater than 75mV to the IN, /IN transition. 13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc = Tn - Tn+1, where T is the time between rising edges of the output signal. 14. Total jitter definition: With an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-topeak jitter value. 15. Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean. Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps.
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Precision Edge(R) SY89295U
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, GND = 0, DIN = 100mV, TA = 25C, unless otherwise stated.
Delay vs. D[9:0]
10000 9000 AMPLITUDE (mV) 8000 7000 6000 5000 4000 3000 2000 1000 0 0 900 800 700 600 500 400 300 200 100 500 D[9:0] 1000 0 0 500 1000 1500 2000 2500
Amplitude vs. Frequency
DELAY (ps)
FREQUENCY (MHz)
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TIMING DIAGRAM
/IN IN tpd /Q Q
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VIN, VOUT 800mV (Typ.)
VDIFF_IN, VDIFF_OUT 1.6V (Typ.)
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
INPUT AND OUTPUT STAGES
VCC
VCC
VCC
75k9
/EN LEN
IN
VBB
SETMIN SETMAX
Q, CASCADE
/IN
D[0:10]
/Q, /CASCADE
75k9
75k9
75k9
Figure 2a. Differential Input Stage
Figure 2b. Single-Ended Input Stage
Figure 3. LVPECL Output Stage
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OUTPUT INTERFACE APPLICATIONS
+3.3V
+3.3V Q
Z0 = 50 Z0 = 50
R1 130
R1 130
+3.3V
+3.3V
Q
Z0 = 50 Z0 = 50
/Q 50
R2 82 R2 82 VT = VCC --2V
/Q
50 For +2.5V systems R1 = 19
VCC
C (optional) 0.01F
For +2.5V systems R1 = 250, R2 = 62.5
R1
50
Figure 4. Parallel Termination
Figure 5. Y-Termination
+3.3V +3.3V R1 130 Q Z0 = 50 /Q R2 82 R2 82 R4 1.6k R1 1k R3 1k +3.3V
+3.3V
For +2.5V systems R1 = 250, R2 = 62.5, R3 = 1.25k, R4 = 1.2k
Figure 6. Terminating Unused I/O
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APPLICATIONS INFORMATION
For best performance, use good high-frequency layout techniques, filter VCC supplies, and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the SY89295U data inputs and outputs. VBB Reference The VBB pin is an internally generated reference and is available for use only by the SY89295U. When unused, this pin should be left unconnected. Two common uses for VBB are to handle a single-ended PECL input, and to re-bias inputs for AC-coupling applications. If IN and /IN are driven by a single-ended output, VBB is used to bias the unused input. Please refer to Figure 10. The PECL signal driving the SY89295U may optionally be inverted in this case. When the signal is AC-coupled, VBB is used, as shown in Figure 13, to re-bias IN and /IN. This ensures that SY89295U inputs are within acceptable common mode range. In all cases, VBB current sinking or sourcing must be limited to 0.5mA or less. Setting D Input Logic Thresholds In all designs where the SY89295U GND supply is at zero volts, the D inputs can accommodate CMOS and TTL level signals, as well as PECL or LVPECL. Figures 11, 12 and 14 show how to connect VCF and VEF for all possible cases. Cascading Two or more SY89295U may be cascaded in order to extend the range of delays permitted. Each additional SY89295U adds about 3.2ns to the minimum delay and adds another 10240ps to the delay range. Internal cascade circuitry has been included in the SY89295U. Using this internal circuitry, the SY89295U may be cascaded without any external gating. Examples of cascading 2, 3, or 4 SY89295U appear in Figures 7, 8, and 9.
Control Word (11bits)
C[10] D[10] C[9:0]
#1
D[9:0]
#2
IN /IN
Q /Q SETMIN SETMAX
IN /IN /CASCADE CASCADE
Q /Q
Figure 7. Cascading Two SY89295U
Control Word (12bits)
C[11]
D[10]
C[10] C[9:0]
D[10] D[9:0]
#3
#1
#2
IN /IN
Q /Q SETMIN SETMAX
IN /IN
Q
IN /IN /CASCADE CASCADE
Q /Q
/Q SETMIN /CASCADE SETMAX CASCADE
Figure 8. Cascading Three SY89295U
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Precision Edge(R) SY89295U
Control Word (12bits)
C[11] #1 #2
D[10] #3
C[10] C[9:0] Q
D[10] #4 D[9:0] IN /IN /CASCADE CASCADE Q /Q
IN /IN
Q /Q SETMIN SETMAX
IN /IN
Q /Q SETMIN SETMAX
IN /IN
/Q SETMIN /CASCADE SETMAX CASCADE
Figure 9. Cascading Four SY89295U
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INTERFACE APPLICATIONS
VCC 0.01mF LVPECL Input* IN /IN VBB
* 3.3V single-ended only, 2.5V, single-ended is not functional.
Figure 10. Interfacing to a Single-Ended LVPECL Signal
To invert the signal, connect the LVPECL input to /IN and connect VCC to IN.
VCC = +3.3V
VCC = +3.3V VCF VEF LVPECL Signals VCC = +3.3V
D[0:10]
Figure 11. VCF/VEF Biasing for LVPECL Control (D) Input
CMOS Inputs
TTL Inputs
D[0:10]
IN
D[0:10]
VCF 1.5k NC VEF
NC VCF
VCC /IN 50 0.01F 50 VBB
NC VEF
0.01F 0V
0V
Figure 12. VCF/VEF Biasing for CMOS Control (D) Input
Figure 13. Re-Biasing an AC-Coupled Signal
Figure 14. VCF/VEF Biasing for LVTTL Control (D) Input
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY89295U SY89296U Function 2.5/3.3V 1.5GHz Precision LVPECL Programmable Delay 2.5/3.3V 1.5GHz Precision LVPECL Programmable Delay with Fine Tune Control 16-MLF Manufacturing Guidelines Exposed Pad Application Note HBW Solutions Data Sheet Link www.micrel.com/product-info/products/sy89295u.shtml www.micrel.com/product-info/products/sy89296u.shtml www.amkor.com/products/notes_papers/MLF_appnote_0902.pdf http://www.micrel.com/product-info/as/solutions.shtml
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32 LEAD MicroLeadFrameTM (MLF-32)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 32-Pin MLFTM Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management.
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32 LEAD TQFP (T32-1)
Rev. 01
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-011806 hbwhelp@micrel.com or (408) 955-1690
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